Semiconductor memory devices are used in a wide variety of contexts to store user data, device status, program code and data, and the like. Generally, memory devices typically comprise one or more memory cells and associated logic. The memory cells may be fabricated as, for example, capacitors, transistors, a combination thereof, or the like.
FIGS. 1 and 2 illustrate a plan view of one particular type of memory device in which memory cells are arranged in arrays, commonly referred to as a memory array and a cross-section view of a split-gate memory cell, respectively. The memory array includes a floating-gate transistor as the storage device for the individual memory cells. The floating-gate transistor includes a source 114, a drain 116, and a split gate 118. The split gate 118 comprises a gate electrode 120 and a floating gate 122 separated by an inter-gate dielectric 124, which is commonly formed of an oxide and referred to as an inter poly oxide (IPO). The bit line 110 is electrically coupled to the drain, and the source is electrically coupled to a voltage source (not shown) via a conductive layer, such as the polysilicon plug 126. The word line 112 is electrically coupled to the gate electrode 120 and often formed integrally therewith. Adjacent memory cells are typically separated by shallow trench isolations (STI) 128. The STI 128 are generally formed by etching a trench in a substrate and filling the trench with a dielectric material, such as a high-density plasma (HDP) oxide.
It is generally desirable to fabricate the memory cell such that the dielectric material in the STI, referred to as the STI filler, is lower on the cell region side of the STI and higher on the periphery region side of the STI. If the STI filler is too high on the cell region side of the STI, then a poly stringer or residue may result, and if the STI fill is too low on the periphery region side of the STI, then the active region may become pitted or portions of the floating gate may be etched.
Therefore, there is a need for a method of fabricating semiconductor devices having different heights of STI filler at the boundaries of the STI filler.